The 8051 instruction set accesses two basic types of memory, internal and external. Internal memory consists of a register array with possible byte addresses from 0 to 255. The first 128 byte locations typically contain a contiguous block of registers. The remaining 128 byte addresses contain various special function registers (SFRs). These registers are generally not contiguous; that is, there are unused register locations. The unused register locations allow for additional SFRs which many manufacturers provide. The 8051 architecture does permit the contiguous register array from low memory to extend above address 127 and to overlap the SFRs. The memory accesses are identified by the addressing mode used. Direct memory addressing used with addresses 128 to 255 will access the SFRs while indirect memory addressing in this region will access the contiguous memory array.The external memory is divided into separate code and data storage. The addresses for each of these areas are sixteen bits long, for a possible 64k each of data and program memory. Operating on data stored in external memory requires first moving it to internal registers, which in turn requires first setting an internal register to point to that data. Thus it is much faster and more efficient to work with data kept in internal memory than that kept in external memory.
Although programs may address the low address bytes of internal memory as a contiguous block of registers, this area has some other salient features. The first 32 bytes are organized into four eight-byte register banks for fast context switching — Individual bytes within a register bank have special significance within the instruction set. The next sixteen bytes are bit addressable. That is, the 8051 uses instructions that directly read or manipulate individual bits. These bits have potential bit addresses from 0 to 255. The first 128 of these bits are mapped into the sixteen bytes in register addresses 32 to 47. Bit addresses 128 to 255 refer to bits within the special function registers.