The UART appears to applications as a series of registers occupying eight consecutive I/O addresses. Most PCs place COMM1 starting at I/O address 3F8H and COMM2 at 2F8H. Normally COMM1 is on IRQ 4 and COMM2 is on IRQ 3 (although some boards allow this to be changed). The starting address is referred to as the base address. Most of this discussion applies to all of the NS8250-compatible UARTs (including NS8250, NS16450 and 16550). I will use the term UART to refer to all UARTs compatible with the 8250, and NS16550 when necessary to specifically identify that chip (for FIFO-related items).I will use the convention of identifying the bits in a register by numbering the low order bit as 0 and the high order bit as 7, i.e., 7654 3210. I have used the following sources for reference: IBM PS/2 Technical Reference Manual; National Semiconductor Datacomm, LAN, UARTs handbook 1990 edition.
Receiver Buffer Register (RBR) — READ at base address (DLAB bit in MCR must be 0)
This register contains the last character received. If register is not read before next character is received, original character will be lost. On the NS16550, reading this register fetches the next character from the FIFO. Up to 16 characters can be in the FIFO at any time.
Transmitter Holding Register (THR) — WRITE at base address (DLAB bit in MCR must be 0)
Writing a character to this register causes it to be transmitted. If it is overwritten before the character is transmitted in its entirety, both characters will be lost. On the NS16550, writing to this register places the character in the transmit FIFO. Up to 16 characters can be in the FIFO at any time.
Divisor Latch Registers — low byte READ/WRITE at base address, high byte READ/WRITE at base address + 1 (DLAB bit in MCR must be 1 to access either of these registers)
These two registers program the baud rate generator. Some common values are shown in Table 1.
Interrupt Enable Register (IER) — READ/WRITE at base address + 1 (DLAB bit in MCR must be 0)
This register is used to enable different types of interrupts from the UART (see the IIR for a description of the interrupts). Any combination of these interrupts can be enabled by setting the corresponding bit to 1. For interrupts to be actually generated to the main CPU, you must also set Bit 3 of the MCR to turn on the OUT2 signal (this bit is used to mask the UART interrupt on most IBM and compatible serial adapters).
- its 7 - 4: Reserved, always set to 0.
- it 3: Modem Status Interrupt.
- it 2: Receiver Line Status Interrupt.
- it 1: Transmitter Holding Register Empty Interrupt.
- it 0: Received Data Available Interrupt.
Interrupt Identification Register (IIR) — READ at base address + 2
When the UART generates an interrupt, the interrupt identification bits in this register are set to indicate the type of interrupt. If several conditions requiring interrupt occur simultaneously, one interrupt will be generated per condition according to the following priority scheme:Receiver Line Status - Highest
Received Data Available - Second
Transmitter Holding Register Empty - Third
Modem Status - Last
- Bits 7,6 (NS16550 only): These bits are both set to 1 when the FIFO is enabled (FCR bit 0 set to 1). If the FIFO isn't enabled (as will be the case for UARTS prior to NS16550 which don't have a FIFO), both of these bits will be 0.
- Bits 5,4: Reserved, always set to 0
- Bit 3 (NS16550 only): Timeout interrupt — when FIFO is enabled, this bit is set to 1 along with bit 2 to indicate that a timeout interrupt is pending.
- Bits 2,1: Interrupt identification (action in parentheses required to reset interrupt):
11 — Receiver Line Status (read LSR)
10 — Received Data Available (read RBR)
01 — Transmitter Holding Register Empty (read IIR or write THR)
00: Modem Status (read MSR)- Bit 0: Interrupt Pending — 0 = Interrupt pending, 1 = No interrupt pending.
FIFO Control Register (FCR, NS16550 only) - RITE at base address + 2
- Bits 7,6: Receiver FIFO trigger level — 00 = 1 byte, 01 = 4 bytes, 10 = 8 bytes, 11 = 14 bytes
- Bits 4,5: Reserved, always set to 0
- Bit 3: RxRdy/TxRdy pins mode — 0 = normal (mode 0), 1 = mode 1. For most applications, leave this set to 0.
- Bit 2: Xmit Fifo reset — write a 1 to this position to reset Xmit fifo (bit is self-clearing)
- Bit 1: Rcv Fifo reset — write a 1 to this position to reset Rcv fifo (bit is self-clearing)
- Bit 0: Fifo enable — 1 = Fifo enabled, 0 = Fifo disabled
Line Control Register (LCR) - EAD/WRITE at base address + 3
- Bit 7: Divisor Latch Access Bit (DLAB) — must be set to 1 during a read or write operation to gain access to the divisor latches of the baud-rate generator. It must be cleared to 0 to gain access to the Receive Buffer, Transmitter Holding, or Interrupt Enable registers.
- Bit 6: Set break — Set to 1 to generate a continuous 'break' condition on the line.
- Bit 5: Reserved, always set to 0.
- Bits 4 & 3: Parity — 11 = Even parity, 01 = Odd parity, 00 = No parity, 10 = Undefined.
- Bit 2: Stop bits — 0 = 1 stop bit, 1 = 2 stop bits (except for word length of 5 when it is 1 - 1 1/2 stop bits).
- Bits 1 & 0: Word Length: 00 = 5 bits, 01 = 6 bits, 10 = 7 bits, 11 = 8 bits
Modem Control Register (MCR) — READ/WRITE at base address + 4
This register controls output signals from the UART. Bits 1 and 0 control signals going to the modem. A brief description of the normal uses of each signal has been provided, but it should be noted that some modems may not use them in this fashion, and other modems may have to be reconfigured to use the signals this way.
- Bits 7 - 4, 2 Reserved, always 0.
- Bit 2: Controls OUT2 signal. On IBM type serial adapters, must be 1 in order to enable interrupt generation.
- Bit 1: Request To Send (RTS) signal control — Set to 1 when modem software is ready to transmit data, and wait for CTS to go to 1 (provided modem supports RTS/CTS handshaking).
- Bit 0: Data Terminal Ready (DTR) signal control — Set to 1 to indicate that modem software is ready to do business. You can instruct some modems to disconnect from the phone line by momentarily dropping DTR.
Line Status Register (LSR) — READ at base address + 5
This register provides information about the state of the data transfer. When a line status interrupt occurs, you should read this register and examine bits 1 - 4 to determine the cause (and clear the interrupt). For the NS16550, the FIFO contains additional bits corresponding to bits 1 - 4 of the LSR. When the FIFO is enabled, bits 1 - 4 of the LSR will be set according to the character currently being read from the FIFO (which may not be the most recently received character) allowing the modem software to handle line errors as if the FIFO did not exist.
- Bits 7 & 6: Don't Care.
- Bit 5: Transmitter Holding Register Empty Set to 1 when the UART is ready to accept a new character for transmission (a THRE interrupt will also be generated). On the NS16550, this bit will be set only when the transmit FIFO is empty. There is no way to determine the actual number of characters remaining in the transmit FIFO at any time.
- Bit 4: Break interrupt — set to 1 when the received data input is held in the spacing state for longer than a fullword transmission (the total time of start bit + data bits + parity bit (if any) + stop bits).
- Bit 3: Framing Error — set to 1 when the received character did not have a valid stop bit.
- Bit 2: Parity Error — set to 1 when the received character does not have the correct parity bit setting.
- Bit 1: Overrun Error — Set to 1 when the data in the RBR was not read by the modem software before the next character received was transferred into it, destroying the previous character.
- Bit 0: Data Ready — Set to 1 when there is a character available in the RBR to be read (a Received Data Available interrupt will be generated), set to 0 automatically when that character has been read.
Modem Status Register (MSR) — READ at base address + 6
- Bits 7 - 4 indicate the current state of the modem control signals (1 = active, 0 = inactive). Bits 3 - 0 are set to 1 whenever the corresponding modem control signal (in bits 7 - 4) has changed (and a Modem Status interrupt is generated), and are automatically reset to 0 after the MSR has been read. A brief description of the normal uses of each signal has been provided, but it should be noted that some modems may not use them in this fashion, and other modems may have to be reconfigured to use the signals this way.
- Bit 7: Data Carrier Detect (DCD) — set to 1 when the modem has detected a valid carrier signal
- Bit 6: Ring Indication (RI) — set to 1 when the modem detects an incoming ring signal on the telephone line.
- Bit 5: Data Set Ready (DSR) — set to 1 to indicate that the modem is ready.
- Bit 4: Clear To Send (CTS) — set to 1 to indicate that the modem is ready for the UART to transmit data (if RTS/CTS handshaking is supported by the modem).
- Bit 3: Delta DCD
- Bit 2: Delta RI
- Bit 1: Delta DSR
- Bit 0: Delta CTS
Scratch Register — READ/WRITE at base address + 7
This is a general-purpose register available to the modem software for any purpose. It does not affect the UART in any way.