/*****************************************************
DEFINES AND MACROS
*****************************************************/
#if UARTMAIN==1
#define UART_VTYPE
#else
#define UART_VTYPE extern
#endif
/* Returns true if x indicates CTS high */
#define IS_CTS(x) ( (x) & 0x10 )
/* Returns true if x indicates DSR high */
#define IS_DSR(x) ( (x) & 0x20 )
/* Returns true if x indicates RING high */
#define IS_RING(x) ( (x) & 0x40 )
/* Returns true if x indicates DCD high */
#define IS_DCD(x) ( (x) & 0x80 )
/*** Port address offset defines ***/
#define TRANSMIT_REGISTER 0
#define RECEIVE_REGISTER 0
#define DIV_LATCH_LOW_BYTE 0
#define DIV_LATCH_HIGH_BYTE 1
#define INTERRUPT_ENABLE_REGISTER 1
#define INTERRUPT_IDENT_REGISTER 2
#define FIFO_CONTROL_REGISTER 2
#define LINE_CONTROL_REGISTER 3
#define MODEM_CONTROL_REGISTER 4
#define LINE_STATUS_REGISTER 5
#define MODEM_STATUS_REGISTER 6
/*** Defines for fifo control register ***/
/* To reset the FIFO at the end of program */
#define FCR_RESET_FIFO 0x00
/* To enable the FIFO */
#define FCR_ENABLE_FIFO 0x01
/* To flush the receive FIFO */
#define FCR_FLUSH_RCV_FIFO 0x02
/* To flush the transmit FIFO */
#define FCR_FLUSH_XMIT_FIFO 0x04
/* Receive interrupt triggered when 1 byte in FIFO */
#define FCR_RCV_TRIG_1 0x00
/* Receive interrupt triggered when 4 bytes in FIFO */
#define FCR_RCV_TRIG_4 0x40
/* Receive interrupt triggered when 8 bytes in FIFO */
#define FCR_RCV_TRIG_8 0x80
/* Receive interrupt triggered when 14 bytes in FIFO */
#define FCR_RCV_TRIG_14 0x0C
/* Enable the FIFO and set
it to generate rcv
interrupts only when fifo
has more than 8 characters */
#define FIFO_ENABLE (FCR_ENABLE_FIFO | FCR_RCV_TRIG_8)
/* If masking Interrupt Identification Register
value with this value equals this value,
then FIFO has been enabled. */
#define IIR_FIFO_ENABLED 0xC0
/* Mask value when checking interrupt status.
Masking the IIR with this value
makes it look the same regardless of FIFO
being on or off. */
#define IIR_MASK 0x07
/* Address of 8259 PIC mask register for IRQ 0 - 7 */
#define R8259A_MASK 0x21
/* Address of 8259 PIC control register for IRQ 0 - 7 */
#define R8259A_CONTROL 0x20
/* Maximum number of characters to transmit
to FIFO at one time. */
#define MAX_TRANFIFO 16
/* Maximum number of characters to read from
the FIFO when the FIFO is below the threshold */
#define MAX_RCVFIFO 12
/* Size of transmit and receive buffers */
#define BUFFER_SIZE 2048
/*** Flag masks for received characters.
If error is indicated, character may not
be valid. If high bit is set, it indicates
an error in the API function. ***/
#define GOOD_CHARACTER 0x0000
#define OVERRUN_ERROR 0x0100
#define PARITY_ERROR 0x0200
#define FRAMING_ERROR 0x0400
#define BREAK_SIGNAL 0x0800
#define RING_INDICATION 0x1000
#define BUFFER_OVERRUN 0x2000
/*****************************************************
STRUCTURE DEFINITIONS
*****************************************************/
/* Structure entry giving information about each port
in the system. */
struct t_port_info
{
/* Circular transmit and receive buffers
for this port */
char a_transmit_buffer[BUFFER_SIZE];
char a_receive_buffer[BUFFER_SIZE*2];
/* Head and tail indices within transmit and
receive buffers. Head always points to
next available slot for character to be
placed in. Tail always points to next
character to be retreived. If head and
tail are equal, then buffer is empty. For
receive buffer, index is a word index.
Receive characters are ordered in pairs
with the first byte being the character and the
second byte being a bitmapped flag. */
unsigned int tx_head;
unsigned int tx_tail;
unsigned int rx_head;
unsigned int rx_tail;
/* Physical base I/O address port's UART chip */
unsigned int base_address;
/* Baud Rate */
unsigned long baud_rate;
/* Number of bits per data character (5-8) */
unsigned char data_bits;
/* Parity (0=None, 1=Odd, 3=Even) */
unsigned char parity;
/* Number of stop bits (1 or 2) */
unsigned char stop_bits;
/* Number of characters read from FIFO without a
receive interrupt. */
unsigned char non_int_chars;
/* Number of characters that can be transmitted on a
single transmitter empty interrupt */
unsigned char max_tx_chars;
/*** Bit fields are all 1 for yes, 0 for no. ***/
/* Will driver obey RTS/CTS protocol signals on
this port? */
unsigned obey_rts_cts:1;
/*** Bit fields representing signal states -
1 = On, 0 = Off ***/
/* DataSet Ready */
unsigned dsr_state:1;
/* Clear To Send */
unsigned cts_state:1;
/* Data Carrier Detect */
unsigned dcd_state:1;
};
/*****************************************************
GLOBAL VARIABLES
*****************************************************/
/* Number of asynchronous serial ports configured
system-wide. */
UART_VTYPE unsigned char g_num_ports;
/* Pointer to calloc'ed array of port information
structures. One for each configured port in the
system. During initialization each port will be
assigned a sequential number from 1 to g_num_ports
(0 is not used) which will be its position within
this array. Ports are accessed as
gp_port_info[port_nbr-1]. */
UART_VTYPE struct t_port_info *gp_port_info;
/* IRQ (Interrupt ReQuest line) number used by
UART(s). Must be between 3 and 7 */
UART_VTYPE unsigned int g_uart_irq;
/*****************************************************
FUNCTION PROTOTYPES
*****************************************************/
void interrupt far Asynch_driver(void);
int Test_for_asynch_port( unsigned int port_address,
unsigned int irq_level );
void interrupt far Catch_asynch_test_interrupt(void);
int Init_UART(void);
void Exit_UART(void);
int Send_char(unsigned int port_number,
unsigned char tx_char);
int Read_char(unsigned int port_number);
/* End of File */